A couple of weeks back we held a talk at Science House on Chip Design, led by guest speaker Lawrence Chernin. Lawrence gave a fascinating talk on the subject, starting with the basics – semiconductor materials and transistors – and building up to the remarkably complex field of chip design, where many thousands, millions or even billions of transistors are arranged into optimized layouts resulting in the chips found in our iPhones, laptops, and digital cameras.
The talk wouldn’t have been so interesting if Lawrence didn’t have such unique and exciting stories to tell about his own experiences in the field. A former astrophysicist with a PhD from Harvard University, Lawrence spent his early career researching star formation and supersonic flows. After a three year stint at Berkeley, Lawrence was drawn into the booming high tech field in nearby Silicon Valley. Below, Lawrence writes about his adventures in the field.

Lawrence explains how transistors are built
Chip Design Adventures in Silicon Valley
by Lawrence Chernin
My first job in Silicon Valley was at Hitachi Semiconductor (now part of Renesas), and I considered myself quite lucky to have been given this opportunity since almost all of my studies and academic work before that were in astronomy… As you can imagine – I’ve been asked over a hundred times, “well what does chip design have to do with astronomy?” Nothing really. By fluke I had met someone at a friend’s barbeque and he invited me to come in and talk to his boss the following week. At that time I had a position at Berkeley which ended in three months. I did have another postdoc lined up, but I was ready for a bigger change – so I thought “what the heck, let’s find out more about chips!” The next morning I did the sixty mile drive down the I-80/880 to Hitachi in San Jose.
The Hitachi interview was like nothing I ever expected. I spoke with several interviewers who asked me questions about the kind of astronomy research I had done, and then one guy recommended a few of the standard textbooks on chip design (e.g. Weste and Eshragian, see below). After two hours, the group manager came in and asked if I would come back tomorrow and sign their offer letter! Wow, that was nothing like I’d ever experienced before. Most academic job prospects had a hundred applications for each position. Also I had been exploring alternative careers for several months and even had a first round interview at McKinsey – which I badly flunked, as well as a couple of interviews with financial quant firms in which I fared no better.
So after glancing at the pretty picture in chip design textbook in one of the Silicon Valley tech bookstores the next day, I drove back down to San Jose and signed the offer letter and gave my notice at Berkeley.
The first project I had involved transistor modeling, but I was given plenty of time to read up on the subject and bring myself up to speed. There were several good textbooks on the subject, as well as internal publications. Transistor models are current – voltage equations that account for the behavior of a transistor. These equations are then inserted into large scale computer simulations which may model a specific chip functional unit like a memory, or perhaps even the entire chip. A program called “Spice” and it’s numerous variations were used for this purpose. The usual tradeoff becomes accuracy vs runtime vs circuit size, and this is the task of the engineer to determine. My task was to find the highest accuracy of the model given the data and measured parameter bin size, and also to consider the boundary conditions and the continuity of the derivatives.

My boss also paid a private consultant to come in for a week and to lecture a few of us on the latest developments. Once we were up to speed this turned into a very exciting project as we were able to improve on some of the Hitachi transistor models. Then I turned my attention to the simulation software package assessment, and became what is known in the field as a CAD (Computer Aided Design) engineer.
After the chip circuit project were completed I was moved into the rapidly growing area of digital chip design automation. This means creating lithography and etching mask patterns for the transistors and wire interconnects that cover the entire chip. A typical chip has three to six mask layers used for the creation of the transistor structure inside the silicon material and then a six or more layers of metals such as copper or aluminum wires on top of it. Mask layers are used to guide etching and deposition process on a silicon wafer.
The transistors of the chip are arrayed in basic circuit gates such as inverters, nands, latches, etc. The circuit gates need to be decomposed out of a software like description of a chip function.
The general name given to this design process is called “place and route”, because it involves placing basic circuit gates in optimal locations on the chip’s silicon surface, in order to minimize the wire connections or “routing” for the circuit. The less the wires, the less the power, the less the heat, and the faster the chip.
So the design companies would purchase large banks of servers to run the design simulations. The computational tasks are broken down to run in parallel using a techniques of threading and multiprocessing as much as possible. one large software design companies that I worked at had 5000 servers that were running simulations 24×7. Most of the time the servers were running quality and regression tests. For a run example, a large CPU chip such as one in a digital camera (typically 40 million transistors or more) could be turned from a software description to a set of mask layers to be fabricated in less than twelve hours on a 4-cpu server.
Most of my years in the industry were spent in the area of place and route software automation, but I also took on a few interesting projects like diagonal chip routing. All digital signal chips are produced in Manhattan routing, but diagonal routing provided another degree of freedom so as to enable further minimization of the total wiring length. This project was so high profile that it even received main stream media coverage, like from the Wall Street Journal. We pasted these clippings on the cubicle walls. However, in the end – after five years, this project was canceled. The main issue had to do with the complexity of manufacture and difficulty of adaptation to the new technology.
So looking back at my time in Silicon Valley, which included several very highly rated start ups, one in fact was more highly rated than Google in 2001, but unlike Google, my startup became just a short historical footnote. I rode the roller coaster of the ups and downs of the chip industry, and it was quite an adventure.

Inside an iPhone
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:REFERENCE DATA:
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Large Semiconductor Chip Manufacturing Companies:
Intel, IBM, Samsung, TSMC, Amd, NEC, Toshiba, Renesas
Large Chip Design Companies, but not also manufacturers:
Qualcomm, Sun (Oracle), Apple
Large Companies in Chip Design Software:
Synopsys, Cadence, Mentor Graphics, Magma.
Philadelphia Semiconductor Index tracks 18 largest semiconductor companies: SOXX
http://finance.yahoo.com/echarts?s=^SOXX
Online Chip Design References:
http://www.anandtech.com/mac/showdoc.aspx?i=3026&p=3
http://en.wikipedia.org/wiki/Verilog
http://jas.eng.buffalo.edu/courses/ee549/cadence/Cadence_tutorial.pdf
Textbook that I learned from:
Principles of CMOS VLSI Design, by Weste and Eshragian.
http://search.barnesandnoble.com/Principles-of-CMOS-VLSI-Design/Neil-HE-Weste/e/9780201533767